Boosting the Accuracy of Analog Test Coverage Computation through Statistical Tolerance Analysis

Increasing numbers of analog components in today’s systems necessitate system level test composition methods that utilize onchip capabilities rather than solely relying on costly DFT approaches. We outline a tolerance analysis methodology for test signal propagation to be utilized in hierarchical test generation for analog circuits. A detailed justification of this proposed novel tolerance analysis methodology is undertaken by comparing our results with detailed SPICE Monte-Carlo simulation data on several combinations of analog modules. The results of our experiments confirm the high accuracy and efficiency of the proposed tolerance analysis methodology.